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automotive power data sheet - rev 1.0, 2015-03-27 TLE82452-3SA 2 channel high-side and low-si de linear solenoid driver ic dragon ic
data sheet 2 rev 1.0, 2015-03-27 - TLE82452-3SA table of contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 input / output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 i/o description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 electrical characteristics i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 battery supply (vbat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.3 load supplies (lsup2, lsup1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.4 analog supplies (vdda and vddaref) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.5 digital supply (vddd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.6 i/o supply (vio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.7 power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.8 charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.9 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.10 power supply modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.11 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.12 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.13 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.2 channel disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.3 channel enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.4 configuration of channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.5 electrical characteristics power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.2 average current setpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.3 dither waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.4 sense resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.5 current controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.6 pwm frequency controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.7 autozero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.8 measurement functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.9 calibration mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.10 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9 protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.2 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table of contents
data sheet 3 rev 1.0, 2015-03-27 - TLE82452-3SA 9.3 overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.4 overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10 diagnosis functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10.2 faultn pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10.3 fault mask bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.4 overcurrent fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.5 open load / switch bypass fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.6 supply out of range fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.7 crc fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.8 regulator error fault (rex) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.9 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.1 description of interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.2 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.3 electrical characteristics spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12 spi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12.1 description of protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12.2 icvid register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12.3 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 12.4 diagnosis register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 12.5 clk-divider register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.6 calibration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.7 setpoint register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.8 dither register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 12.9 integrator limit register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 12.10 pwm period register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 12.11 integrator threshold &open on register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12.12 autozero register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12.13 feedback register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 13 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 13.1 further application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 14 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
pg-dso-36 type package marking TLE82452-3SA pg-dso-36 TLE82452-3SA data sheet 4 rev 1.0, 2015-03-27 - 2 channel high-side and low -side linear solenoid driver ic dragon ic TLE82452-3SA 1overview features ? two independent low side / high side configurable channels ? integrated half-bridge power stages ?r on (max) = 250 m @ tj = 150 c ? integrated sense resistor wit h internal tcr compensation ? load current measurement range = 0 ma to 1500 ma (typical) ? current setpoint resolution = 11 bits ? current control accuracy ? +/- 5ma for load currents less than 500 ma ? +/- 1% for load currents greater than 500 ma ? excellent immunity to large load supply voltage changes ? integrated dither generator with pr ogrammable amplitude & frequency ? spi interface for output contro l, diagnosis, and configuration ? independent thermal shutdown for each channel ? open load, switch bypass, and overcurrent protection and diagnosis for each channel ? programmable slew rate control for reduced emi ? green product (rohs compliant) ? aec qualified description the TLE82452-3SA is a flexible, monolit hic solenoid driver ic designed for the control of linear solenoids in automatic transmission, electronic stab ility control, and active suspension applications. the two channels can be used as either lowside or highside drivers in any combinat ion.the device includes the dr ive transistor, recirculation transistor, and current sensing resistor; minimizi ng the number of required external components. this device is capable of regulating the average current flow in a load up to 1500 ma, depending on the dither settings and the load characteristics, with 11 bits re solution. a triangular dither waveform generator, when enabled, superimposes a triangular waveform with pr ogrammable amplitude and frequency on the programmed current setpoint. a 32 bit spi interface is used to co ntrol the two channels and to monitor th e status of the diagnostic functions. an active low reset input, resn, is used to disable all of the channels and reset the internal registers to the default values. an active high enable pin, en, is used to enable or disable the operation of the output channels. when the en pin is low, the channels are disabled, and the spi interf ace is fully functional. a faul t output pin is provided to generate a signal that can be used as an external interrupt to the microcon troller whenever a fault is detected.
data sheet 5 rev 1.0, 2015-03-27 - TLE82452-3SA block diagram 2 block diagram figure 1 block diagram channel 2 block_diagram.vsd load2 channel 1 control logic gate control load current limitation gate control load current limitation load current sense power supply & under - voltage detection logic faultn en resn so sck si csn vio vdda spi tm clk vddd gnda gndd vbat lsup 1 load1 lsup 2 gndp2 gndp1 gndp tst0 hsls1 hsls2 charge pump cpc1l cpc1h cpc2l cpc2h cpout vddaref gndaref temperature sensor diagnostics watchdog tmo 1 tmo 2 lsup
data sheet 6 rev 1.0, 2015-03-27 - TLE82452-3SA pin configuration 3 pin configuration 3.1 pin assignment figure 2 pin configuration 3.2 pin definitions and functions pin symbol function 1gndp ground; ground connection. chip damaged if connection lost. 2nu not used no connection should be made to this pin. 3lsup supply voltage; connect to switched battery voltage with reverse protection diode and filter against emc 4tst0 test pin; connect to gnd or +5v 5gndp1 ground; ground connection for channel 1 power stage. chip damaged if connection lost. 6load1 output connect a ceramic capacitor of <= 10 nf to gnd for esd protection. 7lsup1 supply voltage; supplies channel 1. connect to switched battery voltage with reverse protection diode and filter against emc. pinout.vsd clk tm en resn faultn vddaref vdda vddd tmo1 tmo2 gndp1 load1 lsup1 hsls1 tst0 gndp nu lsup sck csn si so vio gndaref gnda gndd cpout cpc2l cpc2h cpc1l cpc1h vbat hsls2 gndp2 load2 lsup2 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 136 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
data sheet 7 rev 1.0, 2015-03-27 - TLE82452-3SA pin configuration 8 hsls1 control input; digital input. connect to ground fo r high-side configuration. connect to +5v or vbat for low-side configuration. 9gndp2 ground; ground connection for channel 2 power stage. chip damaged if connection lost. 10 load2 output; connect a ceramic capacitor of <= 10 nf to gnd for esd protection. 11 lsup2 supply; supplies channel 2. connect to switched battery voltage with reverse protection diode and filter against emc. 12 hsls2 control input; digital input. connect to ground fo r high-side configuration. connect to +5v or vbat for low-side configuration. 13 vbat supply voltage; connected to battery voltage with reverse protection diode and filter against emc. 14 cpc1h charge pump; for internal charge pump; connect a ceramic capacitor between cpc1h and cpc1l. 15 cpc1l charge pump; for internal charge pump; connect a ceramic capacitor between cpc1h and cpc1l. 16 cpc2h charge pump; for internal charge pump; connect a ceramic capacitor between cpc2h and cpc2l. 17 cpc2l charge pump; for internal charge pump; connect a ceramic capacitor between cpc2h and cpc2l. 18 cpout charge pump output for internal charge pump; connect a ceramic storage capacitor from this pin to vbat. this pin should not be connected to other external components or used as a supply for other circuits. 19 tm test pin; connect to gnd. 20 en control input; digital input: 3.3v or 5.0v logi c levels. active high enable input. 21 resn control input; digital input: 3.3v or 5.0v logi c levels. active low reset input. 22 faultn status output; open drain output. in case not used, keep open. 23 tmo1 test pin; connect to gnd. 24 vddaref supply voltage; supplies analog circuits. connect to 5.0v supply voltage. 25 gndaref ground; ground connection for analog circuits. 26 gnda ground; ground connection for analog circuits. 27 vdda supply voltage; supplies analog circuits. connect to 5.0v supply voltage. 28 gndd ground; ground connection for digital circuits. 29 vddd supply voltage; supplies digital circuits. con nect to 5.0v supply voltage 30 tmo2 test pin; connect to gnd. 31 clk clock input; main system clock. 32 csn spi chip select input; digital input: 3.3v or 5.0v logic levels. 33 sck spi clock input; digital input: 3.3v or 5.0v logic levels. 34 si spi input; digital input: 3.3v or 5.0v logic levels. 35 so spi output; push pull output compatible to 3.3 v and 5.0 v logic levels. pin symbol function
data sheet 8 rev 1.0, 2015-03-27 - TLE82452-3SA pin configuration 36 vio io supply; connected to 3.3 v or 5.0 v supply. cooling tab gnd cooling tab; interna lly connected to gnd. pin symbol function
data sheet 9 rev 1.0, 2015-03-27 - TLE82452-3SA general product characteristics 4 general product characteristics 4.1 absolute maximum ratings table 1 absolute maximum ratings 1) t j = -40 c to +150 c; all voltages with respect to ground (gndd), positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. voltages supply voltage v bat -0.3 ? 45 v ? p_4.1.1 load supply voltage v lsup -0.3 ? 45 v ? p_4.1.2 digital, analog, and io supply voltage v ddd , v dda , v ddaref , v io -0.3 ? 5.5 v with respect to gndd, gnda, gndaref, and gndpx p_4.1.3 input voltage; sck, csn, si, resn, en, tm, clk v inlv -0.3 ? v ddd + 0.3 2) v? p_4.1.4 input voltage; hsls1, and hsls2 v hslsx -0.3 ? v bat + 0.3 3) v? p_4.1.6 open drain output; faultn v faultn -0.3 ? v io + 0.3 2) v? p_4.1.9 push pull output; so v so -0.3 ? v io + 0.3 2) v ? p_4.1.10 voltage; loadx v load -2 ? v x + 5 4) v |i i | < 1.6 a p_4.1.11 voltage; cpout v cpout v bat - 0.3 ? 50 v ? p_4.1.12 maximum voltage; cpc1l, cpc2l v cpcxl -0.3 ? 50 v ? p_4.1.13 maximum voltage; cpc1h, cpc2h v cpcxh -0.3 ? 50 v ? p_4.1.14 maximum voltage; gndpx v gndp -0.3 ? 1.0 v with respect to gndd p_4.1.15 maximum voltage; gnda, gndaref v gnd -0.3 ? 0.3 v with respect to gndd p_4.1.16 currents output current i -1.6 ? 1.6 a dc 5) p_4.1.17 output current, faultn pin i faultn 0 ? 20 ma dc p_4.1.18 output current, so pin i so -20 ? 20 ma dc p_4.1.19
data sheet 10 rev 1.0, 2015-03-27 - TLE82452-3SA general product characteristics notes 1. stresses above the ones listed here may cause perma nent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. integrated protection func tions are designed to prevent ic destructi on under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. pr otection functi ons are not designed for continuous repetitive operation. input current; sck, csn, si, resn, en, tm, clk i in -5 ? 5 ma maximum allowable forward and reverse current through the esd structure p_4.1.20 temperatures junction temperature t j -40 ? 150 c continuous operation p_4.1.21 storage temperature t stg -55 ? 150 c ? p_4.1.22 esd susceptibility esd resistivity to gnd v esd -2 ? 2 kv hbm 6) p_4.1.23 esd resistivity all pins 7) v esd -2 ? 2 kv hbm 6) p_4.1.24 esd resistivity to gnd v esd -500 ? 500 v cdm 8) p_4.1.25 esd resistivity pin 1, 18, 19, 36 (corner pins) v esd1,18,19,36 -750 ? 750 v cdm 8) p_4.1.26 1) not subject to production test, specified by design. 2) voltage must not exceed 5.5v. 3) voltage must not exceed 45.0v. 4) vloadx - vgndpx and vlsupx-vloadx must not exceed 45.0v. 5) compliant to short circuit requirements according to aec-q100-012. 6) esd susceptibility, hbm acco rding to eia/jesd 22-a114b. 7) pin vbat vs. pin cpc1h : +/- 1.5kv. 8) esd susceptibility, charged device model ?cdm? eia/jesd22-c101 or esda stm5.3.1 table 1 absolute maximum ratings 1) (cont?d) t j = -40 c to +150 c; all voltages with respect to ground (gndd), positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
data sheet 11 rev 1.0, 2015-03-27 - TLE82452-3SA general product characteristics 4.2 functional range note: within the functional or operating range, the ic operat es as described in the circuit description. the electrical characteristics are specif ied within the conditions given in th e electrical char acteristics table. table 2 functional range parameter symbol values unit note / test condition number min. typ. max. supply voltage range for nominal operation v batnom 8 ? 17 v ? p_4.2.1 extended supply voltage range for operation v bat(ext) , v lsup_uv(ext) v lsup_uv ? 8 v parameter deviations possible p_4.2.2 extended supply voltage range for operation v bat(ext) , v lsup(ext) 17 ? 40 v parameter deviations possible p_4.2.3 vbat supply voltage transients slew rate d v bat /d t -1 ? 1 v/s 1) ? 1) not subject to production test, specified by design. p_4.2.4 load supply voltage v lsup 8? v bat +0.3 2) 2) vlsupx - gndd must not exceed 45.0v. v ? p_4.2.5 load supply voltage transients slew rate d v lsup /d t -1 ? 1 v/s 1) ? p_4.2.6 digital supply voltage v vddd 4.75 ? 5.25 v p_4.2.7 analog supply voltage v vdda , v vddaref 4.75 ? 5.25 v p_4.2.8 ground offset voltage; gnda, gndaref v gnd -0.1 ? 0.1 v with respect to gndd p_4.2.9 io supply voltage v io 3.0 ? 5.25 v ? p_4.2.10 voltage (static); loadx v loadx -0.3 ? v + 0.3 v ? p_4.2.11 voltage (dynamic); loadx v loadx -2 ? v + 5 v |i i | < 1.6 a p_4.2.12 system clock frequency f sys 4?6 mhz f sys = f clk / f sys_div p_4.2.13 clk pin frequency f clk 8 ? 40 mhz ? p_4.2.14 spi clock frequency f sck ? ? 8 mhz ? p_4.2.15 loadx pwm frequency f load 100 ? 4000 hz dependent on solenoid characteristics p_4.2.16 junction temperature t j -40 ? 150 c ? p_4.2.17
data sheet 12 rev 1.0, 2015-03-27 - TLE82452-3SA general product characteristics 4.3 thermal resistance note: this thermal data was generated in accordance wit h jedec jesd51 standards. fo r more information, go to www.jedec.org . table 3 thermal resistance parameter symbol values unit note / test condition number min. typ. max. junction to case 1) 1) not subject to production test, specified by design. r thjc ??2k/w? p_4.3.1 junction to ambient r thja ?15?k/w 2) 2) specified r thja value is according to jedec jesd51-2,-5,-7 at natural convection on fr4 2s2p board; the product (chip+package) was simulated on a 76.2 114.3 1.5 mm boar d with 2 inner copper layers (2 70 mm cu, 2 35 mm cu). where applicable a thermal via array under the exposed pad contacted the first inner copper layer. p_4.3.2
data sheet 13 rev 1.0, 2015-03-27 - TLE82452-3SA input / output 5 input / output 5.1 i/o description the clk pin must be connected to a precise clock signal. this clock is used by the internal analog to digital converters and by the internal logic. a small internal pull down current will keep the volt age on this pin near ground when the pin is open. the device includes a programmable divider to generate the internal system clock from the clk pin signal. this divider ratio is programmed in the clk-divider register by the spi interface. the output stages cannot be enabled unt il this field has been written. an internal watchdog circuit will hold the device in an inte rnal reset state if the dela y between rising edges on the clk pin is greater than the threshold time, t clk_mss . the watchdog is initially disa bled when the device exits the reset state. the watchdog is enabled by setting the wden bit in the clk-divider register. if the watchdog is enabled, there are no settings which can prevent the fault pin being pulled low during a wd event. until the watchdog is enabled, the output stages are di sabled. once the watchdog f unction is enabled, a missing clk signal will set the watchdog status bit in the ic version register, set the faultn pin to a logic low state, disable the output stages, and cause the device to enter an internal reset stat e. if the clk sig nal is missing, the spi response from the devi ce will always be the response to an ic ver sion register read command. if the clk signal returns after the watchdog functi on has triggered, the spi response to a specific register read command will be the reset value of the specific regi ster, except of the icvid register that is indicating the watchdog timeout fault. be aware that the clk-di vider is reset to 8 when the clk is lost and than returns, which affects the system clock frequency ( f sys = f clk /8) and thus the transfer delay time (see p_11.3.6). in both cases it is not possib le to write to any spi register. to return to normal operation and exit this internal reset state the device must be reset externally by the resn pin or an power on reset must be performed. the en pin is used to enable / disable the output stages. if the en pin is lo w, all of the channels are disabled and (when the fault mask bit fme = 1) the faultn pin is pu lled low. the spi interface remains functional. however, when the en pin is low, the en bits in the set-point registers are cleared. the en pin can be connected to a general purpose output pin of the microcont roller or to an output of a safing circuit. however, all other spi register settings remain unchanged. after the en pin goes high the en bits in the set point registers remain 0 until they are changed to 1. the en bits will immediately return to 0 if the en pin is low. the resn pin is the reset input for the device. if the resn pin is low, the device is held in an internal reset state, the faultn pin is held low, and the spi interface is disabled . an internal pull down current source will hold the resn pin low in case the pin is open. the faultn pin is an open drain output. this pin is pulled low when a fault is detected by the diagnosis circuit or when the device is in an internal reset state. an extern al resistor should be connect ed between this pin and the vio supply. the si, so, csn, and sclk pins comprise the spi interface. see chapter 11 and chapter 12 for details.
data sheet 14 rev 1.0, 2015-03-27 - TLE82452-3SA input / output figure 3 clock divider first clock divider second clock divider f clk f sys divider = 2, 4, 6, or 8 (default = 8) divider = (m+1)*2 n f dith clk logic circuits adc dither circuit block 6 mhz (max)
data sheet 15 rev 1.0, 2015-03-27 - TLE82452-3SA input / output 5.2 electrical characteristics i/o table 4 electrical characteristics: v bat = 8 v to 17 v, v ddx = 4.75 v to 5.25 v, t j = -40 c to +150 c, all volt ages with respect to ground (gndd), positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. control inputs en, resn, csn, si, sck, clk input threshold - low v in_l 0.8 ? ? v v in increasing p_5.2.1 input threshold - high v in_h ??2.0v v in decreasing p_5.2.2 input hysteresis v in_hys ? 50 mv p_5.2.3 pull up current - csn i pu -50 ? -10 a p_5.2.4 pull down current - en, si, sck, clk, resn i pd 10 ? 50 a p_5.2.5 output so output low-level voltage v so_l 0?0.5v i so = 0.5ma p_5.2.6 output high-level voltage v so_h v io - 0.5 ? v io v i so = -0.5ma, 3.0v < v io < 5.5v p_5.2.7 output tri-state leakage current i so_off -10 ? 10 a v csn = v io p_5.2.8 output faultn output low-level voltage v flt_l 0?0.4v i flt = 2ma p_5.2.9 output tri-state leakage current v flt_off -10 ? 10 a p_5.2.10
data sheet 16 rev 1.0, 2015-03-27 - TLE82452-3SA power supply 6 power supply 6.1 overview the TLE82452-3SA has multiple supply pins. the internal circuits are powered by three +5.0 v supply pins; vddd, vdda, and vddaref; and by on e battery pin, vbat. a separate supply pin, vio, can be connected to either a 3.3 v or 5 v supply depending on the logic levels of the interfaced microcontroller i/o signals. the device includes a charge pump circ uit which generates a supply voltag e greater than vbat. 6.2 battery supply (vbat) this pin is the supply for the internal charge pump and mu st be connected to the reverse polarity protected battery voltage supply. for correct operation the voltage on this pin must not be lower than the voltage on any of the lsupx pins. this pin is also used by the overvoltage detection circuit. 6.3 load supplies (lsup2, lsup1) these pins are the supply pins for the two output stages. if the voltage on one of these pins is lower than the lsup under voltage threshold, the respective power stage is di sabled and the respective uvx fault bit is set in the diagnosis register. the lsup pins of unus ed channels must be connected to vbat. 6.4 analog supplies (vdda and vddaref) the vdda pin is the supply for the internal analog circuits such as the amplifiers and analog-to-digital converters. the vddaref pin is the supply for the internal bandg ap references. an externally regulated 5.0 vdc +/- 5% supply must be connected to these pins. a ceramic capacitor with a value of 100nf must be connected between each of these pins and ground near the ic. these pins are monitored by a pair of internal comparator s. the internal logic circuits are held in a reset state if the voltage on either of these pi ns is less than the threshold v dda_uv and v ddaref_uv . 6.5 digital supply (vddd) this pin is the supply for all of the in ternal logic circuitry. an externally regulated 5.0 vdc +/- 5% supply must be connected to this pin. a ceramic capac itor with a value of 100nf must be connected between this pin and ground near the ic. this pin is monitored by an internal comparator. the intern al logic circuits are held in a reset state if the voltage on this pin is less than the threshold v ddd_uv . 6.6 i/o supply (vio) this pin is used to supply the pins that interface with t he external microcontroller. th is pin must be connected to a supply with the same voltage, 3.3v or 5.0v, that is used to supply th e peripherals of the microcontroller. 6.7 power on reset an internal power on reset circuit holds the device in a reset state if any of the supplies vddd, vdda, or vddaref is below the respective underv oltage detection threshold. the device is also held in reset if the clock signal on the clk pin is missing or the clock frequency is too low when the clk pin watchdog is enabled. the power on reset is released after the following conditions. all of the supplies are above their respective threshold voltages then a fixed power on reset time ( t por ) elapses. the spi interface can be accessed after the power on reset time.
data sheet 17 rev 1.0, 2015-03-27 - TLE82452-3SA power supply the fault bit ?rst? in the diagnosis r egister is set whenever the device exit s the reset state. this bit is cleared automatically whenever the diagnosis re gister is accessed. the microcontro ller can use this bit to determine if an internal or external reset has occurred. 6.8 charge pump in order to provide low rdson of the high-side mosfet transi stors, a charge pump is used to drive the internal gate voltage above vbat. the dev ice uses a common charge pump for all ch annels. the charge pu mp uses the battery voltage supply connected to the vbat pin. the charge pu mp output voltage at the cpout pin is regulated to typically 11v ab ove the voltage at the vbat pin. the charge pump circuit requires three external capac itors. a reservoir capacitor with a recommended value of 220nf must be co nnected between the cpout pin and the vbat pin. two pump capac itors with recommended values of 27nf must be connected between the cp c1l and cpc1h pins and also between the cpc2l and cpc2h pins. a built in supervisor circuit checks if the char ge pump output voltage is suff icient to control the high- side mosfet transistors. if the vcpout voltage is less than the ch arge pump undervoltage threshold, the output transistors are disabled and the cpuv fault flag is set in the diagnosis register. a separate cpw (charge pump warning) fault bit in the diagnosis r egister is set if the vcpout voltage is below the cp warning threshold voltage. the device will continue to operate normally when the vcpout voltage is between the cpw threshold and the cpuv threshold, however the current contro l accuracy may be outside of the specification limits. 6.9 sleep mode if any one of the vddd, vdda, and vddaref voltage su pplies is below the respective undervoltage threshold, the device enters sleep mode. the current drawn into the vbat pin is reduced during this mode of operation. sleep mode is automatically exited when all of the vddd, vdda, and vddaref supply pins are above the respective undervoltage threshold. the sleep mode has the same effect as a reset and follows the initialization sequence. 6.10 power supply modes the following table describes the operation of the device with all possible power supply modes of vbat, vcpout, vddd, vdda, vddaref, and vio. the ?x? symbol means that the state of this supply does not effect the result (can be either supplied or not supplied) in the specific case.
data sheet 18 rev 1.0, 2015-03-27 - TLE82452-3SA power supply figure 4 power supply mode diagram the x's indicate a don't care condition for all the states below the double line. 1. the faultn pin is low if the fme fault mask bit is set to 1 2. the rst bit in the diagnosis register will be set after the device exits the reset state 3. a missing clk signal will result in a rese t only if the clk watchdog has been enabled 4. the faultn pin is low if the fmx fault mask bit is set to 1 6.11 initialization the following figure illustrates t he initialization sequence for t he device after power-up. the t por cycle begins on the first clk clock cycle after the resn pin transitions from low to high. vddd vdda vddaref resn clk wden vio vcpout - vbat < vddx_uv x x x x x x x sleep mode channel operational spi functional diagnostics functional faultn yes no no no low < vddx_uv x yes no no no low < vddx_uv yes no no no low low x x x x no no no no low > vddx_uv > vddx_uv > vddx_uv high tclk > tclk_mss > 3.0v high x no no no response is icvid no low high tclk < tclk_mss 0v high > cpuv no yes yes input ? yes response is 0000 h > 3.0v high x no no no load faults are detected low (1) yes > 3.0v high no no yes low yes > 3.0v high < cpuv no yes yes > 3.0v high > cpuv no no (channel x only) yes yes no low rst bit high (2) undefined low (4) high (2) high (2) high (2) high (3) unchanged unchanged unchanged unchanged unchanged vbat x x x < vbatov x x > cpuv > vbatov < vbatov vlsup x x x x x x x x x x x x x x x x x x x x > vddx_uv > vddx_uv > vddx_uv > vddx_uv > vddx_uv > vddx_uv x high tclk < tclk_mss > vddx_uv > vddx_uv > vddx_uv high tclk < tclk_mss > vddx_uv > vddx_uv > vddx_uv high tclk < tclk_mss > vddx_uv > vddx_uv > vddx_uv high tclk < tclk_mss > vddx_uv > vddx_uv > vddx_uv > 3.0v high no yes yes yes high unchanged > cpuv < vbatov high tclk < tclk_mss > vddx_uv > vddx_uv > vddx_uv > vlsupuv x x x < vlsupuv > vlsupuv high tclk > tclk_mss > 3.0v low x no no yes no low high (3) x > vddx_uv > vddx_uv > vddx_uv x watchdog fault yes no no no no no no no en x x x high low high high high xx high x no no no no
data sheet 19 rev 1.0, 2015-03-27 - TLE82452-3SA power supply figure 5 initialization sequence apply +5v to each vddx pin and the vio pin apply the clock signal to the clk pin, then transition the resn pin from low to high. wait for the t por timer to elapse the spi bus will begin responding after the t por has elapsed. device is ready to operate write to the clk-divider register via the spi interface. enable the watchdog and set the system clock divider. wait for t wu wake up timer to elapse t wu has elapsed when the az bit returns to 1 in the spi register. faultn pin = high faultn pin = high faultn pin = low faultn pin = low faultn pin = low t wu /ms = 65536/(f sys /khz) + 0.1 see p_6.12.14 t por /ms = 65536/(f clk /khz) see p_6.12.20
data sheet 20 rev 1.0, 2015-03-27 - TLE82452-3SA power supply 6.12 reset if the device needs to be shut down during operation th e resn pin can be pulled low. the resn pin should be held low until the current flowing in the solenoid decays to zero. if the device is restarted with current flowing in the solenoid the au to zero function will enter the value as an of fset, causing an error in the current control. 6.13 electrical characteristics table 5 electrical characteristics: power supply v bat = 8 v to 17 v, v ddx = 4.75 v to 5.25 v, t j = -40 c to +150 c, cpc1 and cpc2 = 27nf cpcout = 220nf, all voltages with respect to ground (gndd), positive cu rrent flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. vbat current consumption normal mode i vbat ? ? 10 ma all channels active p_6.12.1 vbat current consumption sleep mode i vbat_slp ? ? 8 a p_6.12.2 vddd current consumption i vddd ? ? 20 ma p_6.12.3 vdda current consumption i vdda ? ? 13 ma p_6.12.4 vddaref current consumption i vddaref ? ? 4 ma p_6.12.5 vio current consumption i vio ??1 macsn= v io =5.25v p_6.12.6 undervoltage reset (internally generated) - vdda v dda_uv 3.8 ? 4.3 v v dda decreasing p_6.12.7 undervoltage reset (internally generated) - vddaref v ddaref_uv 3.8 ? 4.3 v v ddaref decreasing p_6.12.8 undervoltage reset (internally generated) - vddd v ddd_uv 3.8 ? 4.3 v v ddd decreasing p_6.12.9 undervoltage hysteresis v uv_hys 150 mv p_6.12.10 lsup undervoltage threshold v lsup_uv 4.5 5.5 v p_6.12.11 missing clk clock detection time t clk_mss 2 ? 10 s p_6.12.12 power on reset time initialized with resn t por ??0.1 ms 1) logic circuits are functional after t por timer p_6.12.13 power on reset time initialized with undervoltage reset t por ?? t por =65536/ ( f clk /khz) ms 1) logic circuits are functional after t por timer p_6.12.20
data sheet 21 rev 1.0, 2015-03-27 - TLE82452-3SA power supply attention: voltage ratings for charge pump caps: cpc1/cpc2: vmin =vbatmax + 10v, ccpout: vmin=16v power-on wake-up time t wu ?? t wu =65536/ ( f sys /khz) + 0.1 ms 1) timer starts after writing to the clk-div register, (csn goes high) all supplies are above the uv thresholds and resn pin is high. output stages are functional after t wu 2) p_6.12.14 charge pump charge pump voltage v cp_out v bat +8 ? v bat +13 3) v p_6.12.15 charge pump clock frequency f cp ?65? khz f sys = 6 mhz 4) p_6.12.16 charge pump warning threshold voltage v cpout_w v bat +7 ? v bat + 8.5 v p_6.12.17 charge pump undervoltage threshold voltage v cpout_uv v bat +4.5 ? v bat +5.5 v p_6.12.18 charge pump overvoltage clamp v cpout_ov ? 48.5 ? v p_6.12.19 1) not subject to production test, specified by design. 2) to guarantee a proper autozero result there must not be any i load during power-on wake-up ( chapter 8.7 ). 3) will not exceed v cpout_ov . 4) parameter not subject to product ion test, specified by design. table 5 electrical characteristics: power supply (cont?d) v bat = 8 v to 17 v, v ddx = 4.75 v to 5.25 v, t j = -40 c to +150 c, cpc1 and cpc2 = 27nf cpcout = 220nf, all voltages with respect to ground (gndd), positive cu rrent flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
data sheet 22 rev 1.0, 2015-03-27 - TLE82452-3SA power stages 7 power stages 7.1 overview there are two output channels implemented in this devi ce. the output power stages of each channel consists of a half bridge made up of two n-channel dmos transistors and a current sensing resistor. an internal charge pump generates the voltage required to swit ch the n-channel dmos high-side swit ches. the switches are protected from external failures by built in overcurren t and overtemperature detection circuits. the half bridge arrangement allows th e use of active freewheeling, which reduces the power dissipation of the device. the arrangement also allows each channel to be individually programmed for lowside or highside drive. the output current slew rate of the power stages can be programmed to one of three values by programming the configuration register by spi. figure 6 power stages 7.2 channel disabled when the channel is disabled, both transistors of the half bridge are turned off. the output stage is in a high output impedance state in this condition. the chan nel is disabled if the en pin is 0, or the en bit is 0, or the set point = 0. 7.3 channel enabled when a channel is configured for lowside operation, th e lowside dmos switch is the ?drive? switch and the highside dmos switch is the ?recircula tion? switch. likewise, when a channel is configured for highside operation, the highside dmos switch is the ?drive ? switch and the lowside switch is the ?recirculation? switch. in normal operation, the ?drive? switch is turned on and off with th e duty cycle needed to regulate the solenoid current at the target value. during the time that the ?drive? switch is turned off, the device is in active freewheeling mode. the ?recirculation? switch is turn ed on in this mode to reduce the voltage dr op across the device during recirculation. power stage.vsd lsupx control logic loadx pgndx so sck si csb vio charge pump +5v vbat cpc1l cpc1h cpc2l cpc2h cpout
data sheet 23 rev 1.0, 2015-03-27 - TLE82452-3SA power stages the transistors are controlled in a way that prevents shoot through current during switching, that is the control logic prevents the simultaneous activation of both the ?drive? switch and the ?recir culation? switch. if the en pin is low, the en bit is pulled to 0. if the en pin changes from low to high, the en bit remains unchanged. 7.4 configuration of channels the pins hsls1, and hsls2 are used to configure each channel for highside or lowside operation. the pin must be connected to ground for highside operation and to vbat or + 5v for lowside oper ation. the configuration of each channel can be verified by readi ng the configuration register via spi.
data sheet 24 rev 1.0, 2015-03-27 - TLE82452-3SA power stages 7.5 electrical charact eristics power stages table 6 electrical characteristics: power stages v bat = 8 v to 17 v, v ddx = 4.75 v to 5.25 v, t j = -40 c to +150 c, all volt ages with respect to ground (gndd), positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. lsupx leakage current i lsup_lkg -150 ? 150 a set-point = 0ma 8v < v lsup < v bat + 0.3v p_7.6.1 lsupx leakage current in sleep mode i lsup_lg_slp -50 ? 50 a sleep mode all vddx=0v p_7.6.2 on-state resistance - high side fet r ds(on)_hs ??250m ? t j = 150c; i load = -1.6a p_7.6.3 on-state resistance - low side fet r ds(on)_ls ??250m ? t j = 150c; i load = 1.6a p_7.6.4 loadx leakage current i load_lkg -300 ? 0 a set-point = 0ma 8v < v lsup < v bat + 0.3v; 0v < v load < v lsup p_7.6.5 loadx leakage current in sleep mode i load_lkg_slp -80 ? 80 a p_7.6.6 current rise and fall times - sr0 t r0, t f0, ?1 1) 1) not subject to production test, specified by design. ?s i load = 1.4a; 8v < v lsup < v bat + 0.3v; 20% to 80% i lsup & i gndp p_7.6.7 current rise and fall times - sr1 t r1, t f1 ?0.5 1) ?s i load = 1.4a; 8v < v lsup < v bat + 0.3v; 20% to 80% i lsup & i gndp p_7.6.8 current rise and fall times t r2, t f2 ?2 1) ?s i load = 1.4a; 8v < v lsup < v bat + 0.3v; 20% to 80% i lsup & i gndp p_7.6.9 voltage slew rate sr0 ? 5 ? v/s p_7.6.10 voltage slew rate sr1 ? 10 ? v/s p_7.6.11 voltage slew rate sr2 ? 2.5 ? v/s p_7.6.12 current sense resistor sense resistor resistance r sense ? 250 380 m ? p_7.6.13
data sheet 25 rev 1.0, 2015-03-27 - TLE82452-3SA current control 8 current control 8.1 overview the device has independent controller blocks for each chan nel. each control loop consists of the average current setpoint input, the dither generator, the load current fe edback path, the controller block, and the output stage. figure 7 controller block diagram 8.2 average current setpoint the average current setpoint value is determined by the contents of the setpoin t register. the relationship between the value of the setpoint register and the average load current is shown in figure 8 .the accuracy band of the current regulation is also shown in figure 8 . the accuracy is specified over the normal operating range of the device (including the full normal operating junction temperature range). an automatic auto-zero feature is included in the device. the auto-zero feature will automat ically measure the offset of the current measurement circuits of each channel after power-up. when a chann el is programmed to regulate current, the offset is compensated by an automatic modifica tion of the setpoint. the content of the spi accessed average current setpoint register is not influenced by the autozero circuit. current control.vsd - setpoint step size dither + + + steps amp controller lsupx loadx gndpx spi
data sheet 26 rev 1.0, 2015-03-27 - TLE82452-3SA current control figure 8 output current transfer function and accuracy 8.3 dither waveform a triangular dither waveform can be added to the average cu rrent setpoint in order to reduce the hysteresis of the driven solenoid valve. the dither waveform is shown in figure 9 . the frequency of the dither waveform is set by programming the steps field in the di ther register. the valu e of the steps field determines the number of dither steps in one quarter of the dither waveform. the ti me duration of each step is set by programming the n and m fields in the clock-divider register. the amplitude of the signal is determined by the contents of the steps field and the contents of the step size field of th e dither register (see figure 9 ). the application software must take care that the product of the steps and stepsize does not exceed 0x03ff hex. when dither is disabled or a new value is entered, the current dither period will be completed. setpoint (decimal) i load_avg (ma) 2047 683 +/- 1% +/- 5 ma 1365
data sheet 27 rev 1.0, 2015-03-27 - TLE82452-3SA current control figure 9 dither waveform the dither waveform can be synchronized to the pwm freq uency by setting the sync bit in the dither register. when the sync bit is set to 0, the triangular dither wa veform is free-running and is asynchronous to the pwm frequency. when the sync bit is set to 1, a new dither period will not start until the start of the next pwm cycle. the start of a pwm cycle period is defined to be when the output stage turns on. the st art of a dither period is defined to be when the dither increases one step above zero on this rising slope of the waveform. current control dither.vsd dither amplitude dither period steps = 3 step size sync = 0 : dither period is independent of switching cycle period sync = 1 : start of dither period is delayed until start of next switching cycle period switching cycle period load current without sync setpoint + dither shape without sync load current with sync setpoint + dither shape with sync sync occurs
data sheet 28 rev 1.0, 2015-03-27 - TLE82452-3SA current control 8.4 sense resistor the current sense resistor is integrated into the device. the initial error and the temperature drift of this resistor are measured and trimmed during the device manufacturing pr ocess.the internal protection circuits are built in a way, that repeated shorts to vbat/gnd will not destroy the internal shunt. 8.5 current controller the current controller regulates the load current by alter natively turning on the drive switch and the recirculation switch. the on time of the drive switch is determined by the integrated pwm period controller. the off time of the transistor is determined by the av erage current controller. when the average load current over the current pwm period is equal to the setpoint during freewheeling, the drive transistor is turned on again and the next pwm cycle is started. figure 10 controller waveforms the controller includes an integrator which integrates the difference between the average load current and the setpoint over the time duration of the pwm cycle. at the start of a pwm cycle, the driving fet is turned on and the recirculation fet is turned off. in this phase of operation, the load current will increa se. when the value of the error integrator exceeds the integrator threshold, the driv ing fet is turned off and t he recirculation fet is turned on. the load current will decrease in this phase of operation. the integrator threshold is adjusted automatically by the internal pwm period controller until the desired pwm period is reached. when the error integrator decreases to 0, the recirculation fet is turned off and the driving fet is turned on to start the next pwm cycle. the integrator can be automatically limit ed by the device after a change in setpoint by setting the auto-limit bit in the setpoint register. the device will limit the integrator output to a small value (+/- 20d) during the setpoint change and then automatically revert back to the normal integrator limit values afte r the setpoint change has been achieved when this bit is set. the bit remains set until changed, or a reset occurs. a ?regulator error? fault bit in the diagnosis register is set when the programmed setpoint current is not reached after 8 pwm cycles after the setpoint register is written. current control waveform.vsd ?on time? ?off time? i setpoint output stage state error integrator threshold load current
data sheet 29 rev 1.0, 2015-03-27 - TLE82452-3SA current control 8.6 pwm frequency controller the integrated pwm frequency controller regulates the pwm frequency using an ?integr al? control loop with a programmable gain, ki. this control loop monitors the actual pwm period and compares it to the pwm period setting in the pwm period register. the error in the pwm period is multiplied by the ga in ki and then integrated at each pwm cycle. the output of the controller adjust s the ?on time? of the pwm signal until the actual pwm period matches the programmed pwm period. ki gains of 1, 1/2, 1/4, 1/8, 1/16, 1/32, and 1/64 can be selected in the pwm period register. the ki value of 1, ki_index =0, has the fastest response time, the ki value of 1/64, ki_index=6, has the slowest response time, but with less overshoot and less ringing. ki_index = 6 is the recommended settin g for initial evaluation. 8.7 autozero each channel has an autozero function which measures and compensates for the offset of analog current measurement circuits. the autozero function is automatically initiated during power-up af ter the first write to the clk-divider register, or with a reset ?resn? after the first write to the cl k-divider register. the function can also be initiated by the user by setting the az start bit in the autozero spi message. the en bit in the setpoint register must be set to 0 to initiate the auto- zero function. this az start bit is automatically cleared by the device when the autozero seque nce is complete. the measured offset of current measurement circuits can be read by the micro controller via the spi message au tozero. autozero functions with the en pin in the high or low state. care must be taken if the device enters autozero while cu rrent is flowing in the solenoid. this can occur if the device is reset or the autozero bit is set, while current is flowing in the solenoids. the current will create an unintended offset. during init ialization or if a reset occurs during operation the device should be held in reset until the current decays to zero. during normal operation an auto zero should not be initiated until the solenoid current decays to zero. the time is determined by the inductance of the solenoid, which can be calculated or measured. 8.8 measurement functions the spi register feedback can be read to access the valu e of the load current measured by the device and the value of the output pwm period. the cfb bit in the di ther register selects betw een two measurement types. when cfb=0, the average current and the switching period are measured over each switching cycle. when cfb=1, the maximum current and minimum currents are measured over a dither cycle. also the number of switching cycles occurring in the last dither cycle is measured. when the cfb bit = 0 and the device is not in calibration mode, the feedback register contains a 12 bit current feedback field. the content of this field represents th e integration of the load current measured by the analog current measurement circuit blocks over the most rec ent switching period. the average load current can be calculated according to the equation i_load_avg = 1.5* current measurement_feedback / period measurement feedback. when the cfb bit = 0 and the device is not in calibration mode, the actual output fr equency of each channel can be determined by reading the 12 bit period feedback fi eld in the feedback register. this field contains the number of system clocks (fsys) counted during the most recently completed pwm period divided by 16, this is the same resolution as the pwm set register. when the cfb bit = 1 and the device is not in calibrati on mode, the feedback register contains two 8 bit current feedback (cfb) fields. the contents of these fields re present the minimum and maximum load current measured by the analog current measurement circuit blocks over t he most recent dither cycl e when dither is enabled. otherwise, these fields contain the minimum and maximum load current va lues since the last read of the feedback register. i min and i max = 1.5* readout / 127. when the cfb bit = 1 and the device is not in calibration mode, the feedback register contains an 8 bit field which contains the number of full switching cycles in th e last dither cycle. this information can be used by the
data sheet 30 rev 1.0, 2015-03-27 - TLE82452-3SA current control microcontroller to calculate the average switching cycle period over a dither period. if dither is disabled, the contents of this register is 0. the contents of the feedback registers are 0 when the re spective channel is not operating. the number of pwm cycles per dither cycle value is 0 if dither is disabled. 8.9 calibration mode in case the accuracy of the current regulation must be improved by module calibration, the TLE82452-3SA device includes a calibration mode of operation. in order to enter calibration mode, the cm bit in the calibration register must be set by writing a 1 to this bit location. calibration mode will not be entered unless the setpoint for all two channels are zero and the en enable bit (in the se tpoint register) is set to 1. if one or more of the channels is not off and a 1 is written to the cm bit, th e write command is ig nored and the cm bi t will remain at 0. in the calibration mode of operation, the individual transistors of the output stages can be controlled by writing to the calx bits in the calibration r egister. the resulting outpu t current will be measured by the device and can be monitored by reading the feedback register. when the device is in calibration mode, the feedback register contains a 16 bit field which repres ents the average load current measured during the calibration. ical = 1.5 * readout / 65535. the current feedback register is not va lid if the pwm period is set to 0x00 hex in the pwm register. current limitation is not active during calibration mode. exceeding 1.5 a may damage the device.
data sheet 31 rev 1.0, 2015-03-27 - TLE82452-3SA current control 8.10 electrical characteristics table 7 electrical characteristics: current control v bat = 8 v to 17 v, v ddx = 4.75 v to 5.25 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. average current regulation current measurement range i meas 0 ? 1500 1) 1) the maximum obtainable average current value is dependent on the chosen pwm frequency, the chosen dither amplitude, and the load impedance. ma target p_8.10.1 current setpoint resolution i spres ? 1500 / 2047 ? ma p_8.10.2 output current accuracy i spaccl1 -5 ? 5 ma 0a < i load < 0.5a -40c < t j < 125c p_8.10.3 output current accuracy i spacch1 -1 ? 1 % 0.5a< i load <1.5a -40c < t j < 125c p_8.10.4 output current accuracy i spaccl2 -7.5 ? 7.5 ma 0a < i load < 0.5a -40c < t j < 150c p_8.10.5 output current accuracy i spacch2 -1.5 ? 1.5 % 0.5a< i load <1.5a -40c < t j < 150c p_8.10.6 accuracy lifetime drift ?? 0.25% ?? 2) 2) this value corresponds to the maximum evaluated life time drift according to aec-q100 grade 1. p_8.10.7 pwm period control pwm period range t pwm_rng 16 ? 65535 cycles f sys cycles 3) 3) the minimum and maximum achievable pwm frequencies depend on the load characteristics. p_8.10.8 pwm period resolution t pwm_res ? 16 ? cycles /lsb f sys cycles p_8.10.9 dither dither amplitude range i darng 0 ? 46 ma steps = 1 p_8.10.10 dither amplitude resolution i dares ? 0.73 ? ma steps = 1 p_8.10.11 dither period range t drng 0.007 ? 100,00 0 ms p_8.10.12
data sheet 32 rev 1.0, 2015-03-27 - TLE82452-3SA protection functions 9 protection functions 9.1 overview the device provides embedded protection functions whic h are designed to prevent ic destruction under fault conditions described in this datasheet. fault condition s are considered as ?outside? normal operating range. protection functions are neither designed for continuou s nor for repetitive operation. there are overload, overtemperature, and overvoltage protection circuits implemented in this device. figure 11 protection func tions block diagram 9.2 overcurrent protection the load current is limit ed by the device itself in case of overload. an overload can be caused by a short to ground when the channel is configured for high-side operation, or by a short to battery when the channel is configured for low-side operation. the channel is switched off when the overload condition is detecte d, the setpoint and en bit are cleared to 0, and the fault bit is latched in th e diagnosis register. the fault bit is cleared when the diagnosis register is read by an spi access. the channel can be turned on again by re-activating the channel by setting a nonzero average current setpoint. see the diagnostic functions section (section 10) for further description. protection_ block_ diagram.vsd lsupx control logic gate control temperature sensor vb at loadx pgndx overload protection t gate control overload protection spi vref so sck si csb vio
data sheet 33 rev 1.0, 2015-03-27 - TLE82452-3SA protection functions conditions for an overcurrent fault detection 1. i load > i load_lim_h - power stage is disabled immediat ely, independent of ocdt filter 2. i load_lim_l < i load_lim_h - no quick shutoff - overcurrent condition needs to persist for t > t ocdt or - power stage changes its state if t < t ocdt to disable the power stage and issue a fault according to the fault assignment matrix figure 12 high-level short circuit ( i l > i load_lim_h ) table 8 fault assignment matrix configuration of channel location of detected overcurrent olsb ovc ls hs fet x ls ls fet x hs hs fet x hs ls fet x x open load in on x t i load i load_lim_h i load_lim_l ps off & fault bit set
data sheet 34 rev 1.0, 2015-03-27 - TLE82452-3SA protection functions figure 13 ocdt expiration overcurrent detection timer ( i load_lim_l < i load < i load_lim_h ) figure 14 state change of power change before ocdt detection ( i load_lim_l < i load < i load_lim_h ) t i load i load_lim_h i load_lim_l t ocdt ps off & fault bit set t t ocdt i load_lim_h i load_lim_l off on freewheeling off ps off & fault bit set i load
data sheet 35 rev 1.0, 2015-03-27 - TLE82452-3SA protection functions 9.3 overtemperature protection a temperature sensor for each channel is used to swit ch off an overheated channel to prevent destruction. when an overtemperature fault is detected, t he channel is automatically turned off and the setpoints and en bits of all the overtemperature channels are cleared to 0, and the fa ult bit is latched in the diagnosis register. the channel remains off until the channel temperature has decreased by the thermal hysteresis value ? tsd. the channels will remain disabled until the diagnostic register is read and the en bit is set back to 1 and the setpoint is set to >0. a fault bit is latched in the diagnosis register when th e overtemperature fault is detected. the fault remains latched until the diagnosis register has been read and the fault condition is no longer present. figure 15 over temperature timing di agram (high-side configuration) i loadx v loadx junction temp csn si so diag- nosis diag- nosis otx = 0 diag- nosis diag- nosis otx=1 tj < otsd tj > otsd otx diag- nosis diag- nosis otx=1 tj < otsd i > 0ma faultn (fmx = 1) diag- nosis diag- nosis otx=1 diag- nosis diag- nosis otx=0
data sheet 36 rev 1.0, 2015-03-27 - TLE82452-3SA protection functions figure 16 overtemperature timing diagram (low-side configuration) 9.4 overvoltage shutdown this feature is implemented to protec t the internal power transistors from damage due to over voltage on the vbat pin. if the voltage on the vbat pin exceeds the vbat overvoltage threshold an ov ervoltage fault bit will be set in the diagnostic register. this fault bit will be latched until the diagnostic register is read by spi and the overvoltage condition no longer exists. all channels are disabled while the overvoltage condition exists and the setpoints and en bits of all the channels ar e cleared to 0, and the fault bit is latched in the diagno stic register. the channel will remain disabled until the diagnostic register is read and th e en bit is set back to 1 and the setpoint is set to >0. the charge pump output voltage is clamped to approxim ately 50v. the charge pump undervoltage fault (cpuv) may be set before the vbat overvoltage fault bit is se t depending on the rise ti me of the vbat voltage. i loadx v loadx junction temp csn si so diag- nosis diag- nosis otx = 0 diag- nosis diag- nosis otx=1 tj < otsd tj > otsd otx diag- nosis diag- nosis otx=1 tj < otsd i > 0ma faultn (fmx = 1) diag- nosis diag- nosis otx=1 diag- nosis diag- nosis otx=0
data sheet 37 rev 1.0, 2015-03-27 - TLE82452-3SA protection functions 9.5 electrical characteristics table 9 electrical characteristics: protection functions v bat = 8 v to 17 v, v ddx = 4.75 v to 5.25 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. overload protection load current limit | i lim_low | 1) | i lim_high | 2) 1) if this limit is exceede d the ocdt counter starts. 2) this is the quick shutoff limit. 1.8 2.6 3 4.3 4.2 6 a note: operates over range v lsup_uv < v lsup < v bat +0.3v, v ddx_uv < v ddx < 5.5v p_9.5.1 load current limit hysteresis | i lim_high | - | i lim_low | 3) 3) this is the difference between the high and low threshold va lue. it is guaranteed that the high threshold always is higher than the low threshold. 0.8 1.4 2 a p_9.5.6 overcurrent detection filter time t ocdt 20 ? 40 cycles f sys cycles p_9.5.2 overtemperature protection thermal shut down temperature t sd 170? 190c 4) 4) not subject to production test, specified by design. p_9.5.3 thermal hysteresis t sd ?10?c 4) p_9.5.4 overvoltage protection overvoltage threshold on vbat v bat_ov 40 ? 44 v p_9.5.5
data sheet 38 rev 1.0, 2015-03-27 - TLE82452-3SA diagnosis functions 10 diagnosis functions 10.1 overview for diagnosis purposes, the device provides a faultn pin and a diagnosis register accessed through the spi interface. the following table lists the types of load faults which are detected in each mode of operation. figure 17 fault conditions detected in each mode of operation figure 18 fault conditions fo r low-side configuration high_side config off (0 ma) on open load short to battery short to ground low_side config off (0 ma) on yes yes yes yes yes yes yes yes yes yes no no lsupx lo adx gndpx hslsx vdd vbat vbat lsupx lo adx gndpx hslsx vdd vbat vbat lsupx lo adx gndpx hslsx vdd vbat vbat vbat open load short to ground (switch bypass) short to battery (shorted load)
data sheet 39 rev 1.0, 2015-03-27 - TLE82452-3SA diagnosis functions figure 19 fault conditions for high-side configuration 10.2 faultn pin the faultn pin is an open drain output pin. the faultn pins of multiple devices can be connected to form a ?wired and? circuit. the faultn pin can be used to gen erate an external interrupt to the microcontroller whenever a fault is detected. the mi crocontroller must then interrogate the device by the spi interface to determine the type of the fault and the faulted channel number. the faultn pin is pulled low when one of following unmasked faults is detected. ?overcurrent ? overtemperature ? open load in on state ? switch bypass in on state ? resn pin is in low state ? en pin is in low state ? internal reset is active due to vddx undervoltage ? clk pin signal fault ? vbat pin overvoltage ? lsupx pin undervoltage ? wd event certain faults can be masked by setting the appropriate mask bits in the conf iguration spi register. a masked fault has no effect on the faultn pin. during power-up, the faultn pin is held low until the de vice is ready to operate. the faultn pin will transition from low to high automatically after power-up. open load short to battery (switch bypass) short to ground (shorted load) lsupx lo adx gndpx hslsx vbat vbat lsupx lo adx gndpx hslsx vbat lsupx lo adx gndpx hsl sx vbat
data sheet 40 rev 1.0, 2015-03-27 - TLE82452-3SA diagnosis functions 10.3 fault mask bits the configuration register includes fault mask bits which can be used to allow or prevent a fault from activating the faultn pin. setting the fme bit to 1 will cause the faultn pin to be held low whenever the en pin is low. if the fme bit is set to 0, the faultn pin is not affected by the state of the en pin voltage. setting the fmx bit to 1 will cause the faultn pin to be held low whenever a otx, ovcx, uvx, or olsbx fault is detected on the respective c hannel. if the fmx bit is set to 0, the state of the otx, ovcx, uvx, and olsbx fault bits will not affect the state of the faultn pin. 10.4 overcurrent fault the device is protected from a short across the load by an overcurrent shutdown feature when the channel is enabled and the setpoint is >0. when a fault is detected the en bit is set to 0, the setpoint is cleared to 0 and the overcurrent fault bit ovcx is set. the channel will remain disabled until th e diagnostic register is read and the en bit is set back to 1 and the setpoint is set to >0. when an overcurrent fault is detected, the ovcx fault bit is latched. the fault bit is cleared when the diag nosis register is read. the functional range for the short circuit detection depends on the setpoint and the pwm period. figure 20 overcurrent fault in low-side configuration 10.5 open load / switch bypass fault an open load fault and a switch bypass fault can be det ected, but not distinguishable, via the olsb bit alone. an olsb fault can be detected when the setpoint of the faul ted channel is equal to 0 ma (channel off) or when the setpoint is greater than 0 ma (channel operating). while the output is off, both faults can be distinguished using the oloff bit. the switch bypass fault is a short to batte ry fault when the channel is configured as a high-side driver and a short to ground when the channel is configured as a low-side driver. the device detects an open load or switch bypass fault in the operating condition by monitoring the load current. if the load current is below the olsb threshold current fo r a time greater than the olsb delay time (on state), then the olsbx fault bit is set and the channel is disabled. t he olsbx fault bit is latched when the fault occurs, and it is cleared when the diagnosi s register is read and the fault is no longer present. the channel will remain disabled until the diagnostic register is read and the en bit is set back to 1 and the setpoint is set to >0. additional information can be found in the diagnostic and protection functions applications note. normal load diag- nosis ovcx =1 diag- nosis i > 0ma i > 0ma toc diag- nosis ovcx =0 diag- nosis i loadx v loadx load state csn si so diag- nosis diag- nosis ovcx =0 diag- nosis diag- nosis ovcx =1 normal load short to battery ovcx toc diag- nosis diag- nosis ovcx =0 faultn (fmx = 1)
data sheet 41 rev 1.0, 2015-03-27 - TLE82452-3SA diagnosis functions figure 21 olsb fault - on state timing diagram (high-side configuration) figure 22 olsb fault - on state timi ng diagram (low-side configuration) the device detects an open load / switch bypass fault when the channel is turned off by applying a weak current source to the loadx pin and comparing the loadx pin vo ltage to vlsupx/2. a pull up current source or a pull down current sink can be activated by setting the idiagx select field of the configuration register. the programmed current source is automatically enabled when t he setpoint is set to 0 and the en bit in the setpoint register is set to 1. it is disabled when the setpoint is set to a value greater than 0 or the en bit is set to 0. a simplified block diagram of the oloff detection circ uit when the channel is disabled is shown in figure 23 . the oloff fault bit is never latched. the fault bit will be cleared wh en the fault is no longer present. when the channel is disabled and an oloff fault is detecte d, it is possible to discriminate between an open load fault and a switch bypass fault by c hanging the idiag current source. for a high-side configured channel, the pull i loadx v loadx load state csn si so diag- nosis diag- nosis oloffx =0 diag- nosis diag- nosis oloffx =1 normal load open load or switch bypass tolsb_on olsbx diag- nosis normal load faultn (fmx = 1) set-point > 0 i loadx v loadx load state csn si so diag- nosis diag- nosis olsbx =0 olsbx =1 normal load open load or switch bypass tolsb_on olsbx normal load faultn (fmx = 1) diag- nosis diag- nosis diag- nosis set-point > 0
data sheet 42 rev 1.0, 2015-03-27 - TLE82452-3SA diagnosis functions up current source must be initially enabled in order to de tect the oloff fault. once this fault is detected, the pull up current source current can be disabled and the pull down current can be enabled by spi in order to determine if the fault is an open load or a short to battery. the diagnostic currents used are weak, a wait time is needed before the oloff bit is read. t wait = ( v lsup /2) * c load / | i diagmin |. i diagmin is the absolute value of the i diag_upmax or i diag_dnmin depending on which is selected. figure 23 olsb fault - off state block diagram lsupx lo adx gndpx v lsupx i diag_pu i diag_pd v lsupx 2 + - filter ol o ffx logic idi ag c esd
data sheet 43 rev 1.0, 2015-03-27 - TLE82452-3SA diagnosis functions figure 24 open load fault - off state timi ng diagram (high-side configuration) figure 25 open load fault - off state ti ming diagram (low-side configuration) v loadx load state csn si so diag- nosis diag- nosis oloffx =0 diag- nosis diag- nosis oloffx =1 normal load open load ol-offx diag- nosis diag- nosis oloffx =1 pull up diagnostic current is active normal load diag- nosis diag- nosis oloffx =0 diag- nosis oloffx =0 diag- nosis faultn (fmx=1) v loadx load state csn si so diag- nosis diag- nosis oloffx =0 diag- nosis diag- nosis oloffx =1 normal load open load ol-offx diag- nosis diag- nosis oloffx =1 pull down diagnostic cur r ent is active normal load diag- nosis diag- nosis oloff x=0 diag- nosis oloffx =0 diag- nosis faultn (fmx=1)
data sheet 44 rev 1.0, 2015-03-27 - TLE82452-3SA diagnosis functions figure 26 switch bypass fault - off state timing diagram (high-side configuration) figure 27 switch bypass fault - off state timing diagram (low-side configuration) v loadx load state csn si so diag- nosis diag- nosis oloffx =0 diag- nosis diag- nosis oloffx =1 normal load short to battery ol-offx diag- nosis diag- nosis oloffx =1 pull up diagnostic current is active normal load diag- nosis diag- nosis oloffx =0 diag- nosis oloffx =0 diag- nosis faultn (fmx=1) v loadx load state csn si so diag- nosis diag- nosis oloffx =0 diag- nosis diag- nosis oloffx =1 normal load short to ground ol-offx diag- nosis diag- nosis oloffx =1 pull down diagnostic current is active normal load diag- nosis diag- nosis oloffx =0 diag- nosis oloffx =0 diag- nosis faultn (fmx=1)
data sheet 45 rev 1.0, 2015-03-27 - TLE82452-3SA diagnosis functions figure 28 open load fault - off state discriminati on timing diagram (hig h-side configuration) figure 29 open load fault - off state discrimina tion timing diagram ( low-side configuration) v loadx csn si so diag- nosis diag- nosis oloffx =1 diag- nosis diag- nosis oloffx =0 ol-offx diag- nosis oloffx =0 diag- nosis diag current = pull down olsb off current pull up current active pull down current active faultn (fmx=1) v loadx csn si so diag- nosis diag- nosis oloffx =1 diag- nosis diag- nosis oloffx =0 ol-offx diag- nosis oloffx =0 diag- nosis diag current = pull up olsb off current pull down current active pull up current active faultn (fmx=1)
data sheet 46 rev 1.0, 2015-03-27 - TLE82452-3SA diagnosis functions figure 30 switch bypass fault - off state discrimi nation timing diagram (h igh-side configuration) figure 31 switch bypass fault - off state discrimi nation timing diagram (low-side configuration) 10.6 supply out of range fault the lsupx pins, the cpout pin, and the vbat pin are connected to internal monitor circuits which disable the output channels if the pin vo ltage is out of range. the vbat pin is connected to an overvoltage detection circuit block. the cpout and lsupx pins are connected to under voltage detection circuits. when the voltage on these pins exceeds the shutdown threshold, a fault bit is set an d the channel is disabled. the fault bits are latched until the diagnosis register is re ad and the voltage is in the correct range. th e en bits and setpoint are cleared to 0. when a cpuv fault occurs, all channels are disabled, th e en bits and setpoints are cleared to 0. the channels v loadx csn si so diag- nosis diag- nosis oloffx =1 diag- nosis diag- nosis oloffx =1 ol-offx diag- nosis oloffx =1 diag- nosis diag current = pull down olsb off current pull up current active pull down current active faultn (fmx=1) v loadx csn si so diag- nosis diag- nosis oloffx =1 diag- nosis diag- nosis oloffx =1 ol-offx diag- nosis oloffx =1 diag- nosis diag current = pull up olsb off current pull down current active pull up current active faultn (fmx=1)
data sheet 47 rev 1.0, 2015-03-27 - TLE82452-3SA diagnosis functions can be reactivated when the cpuv faul t is not present by reading the diag nosis register and setting the en bits to 1 and set the setpoint to > 0. figure 32 supply out of range fault in high-side configuration i loadx v loadx csn si so diag- nosis diag- nosis ovb = 0 cpuv = 0 lsupuvx=0 diag- nosis diag- nosis ovb, cpuv, lsupuvx vbat < ovsd threshold ovb = 1 cpuv = 1 lsupuvx=1 cpout ? vbat > uv threshold lsupx > uv threshold diag- nosis diag- nosis diag- nosis diag- nosis ovb = 1 cpuv = 1 lsupuvx=1 ovb = 0 cpuv = 0 lsupuvx=0 fault (fmx=1 lsupuvx) and and vbat < ovsd threshold cpout ? vbat > uv threshold lsupx > uv threshold and and vbat > ovsd threshold cpout ? vbat < uv threshold lsupx < uv threshold or or set-point > 0
data sheet 48 rev 1.0, 2015-03-27 - TLE82452-3SA diagnosis functions figure 33 supply out of range fault in low-side configuration 10.7 crc fault the device contains eeprom cells for storing calibration data. these cells are accessed during start up and periodically during operation of the device. a cyclical redundancy checking (crc) feature is included to detect errors in the reading of the eeprom. if an error is detected , the crc error bit will be set in the diagnosis register. all channels will remain oper ational, but the accuracy of the curr ent control may be degraded. the crc fault bit is cleared upon re ading the diagnosis register. 10.8 regulator error fault (rex) the diagnosis register includes a regulator error bit for ea ch channel. this bit is se t when the controller is not able to regulate the load current to the setpoint value for more than 8 consecutive pwm cycles. the re bit is set if the integrator output exceeds the upper or lower limit for more than 8 pwm cycles. the rex fault bits are cleared upon reading the diagnosis register. i loadx v loadx csn si so diag- nosis diag- nosis ovb = 0 cpuv = 0 lsupuvx=0 diag- nosis diag- nosis ovb, cpuv, lsupuvx ovb = 1 cpuv = 1 lsupuvx=1 diag- nosis diag- nosis diag- nosis diag- nosis ovb = 1 cpuv = 1 lsupuvx=1 ovb = 0 cpuv = 0 lsupuvx=0 fault (fmx=1 lsupuvx) vbat < ovsd threshold cpout ? vbat > uv threshold lsupx > uv threshold and and vbat < ovsd threshold cpout ? vbat > uv threshold lsupx > uv threshold and and vbat > ovsd threshold cpout ? vbat < uv threshold lsupx < uv threshold or or set-point > 0
data sheet 49 rev 1.0, 2015-03-27 - TLE82452-3SA diagnosis functions 10.9 electrical characteristics table 10 electrical characteristics: diagnosis v bat = 8 v to 17 v, v ddx = 4.75 v to 5.25 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. shorted load resistance threshold r sl_on 0.5 ? ? ? 1) 1) not subject to production test, specified by design. p_10.9.1 open load - switch bypass threshold current range (on state) i olsb_on 0 ? 375 ma configurable p_10.9.2 open load - switch bypass delay time (on state) t olsb_on ? 8192 ? cycles f sys cycles p_10.9.3 off-state pull up current i diag_up -600 ? -100 a v load < v lsup - 4v p_10.9.4 off-state pull down current i diag_dn 100? 600a v load > 4v p_10.9.5 off-state loadx threshold voltage v load_diag 0.42* v lsup ?0.58* v lsup v independent of v bat voltage p_10.9.6
data sheet 50 rev 1.0, 2015-03-27 - TLE82452-3SA serial peripheral interface (spi) 11 serial peripheral interface (spi) 11.1 description of interface the diagnosis and control communication interface is based on the standard serial peripheral interface (spi). the spi is a full duplex synchronous serial slave interface which uses four signal lines: so, si, sck, and csn. data is transferred by the lines si and so at the data rate given by sck. the fa lling edge of csn indi cates the beginning of a data access. data is sampled in on line si at the falling edge of sck and shifted out on line so at the rising edge of sck. each access must be terminated by a rising edge of csn. a counter ensu res that data is taken only when 32 bits have been transferred. if in one transfer cyc le the number of bits transferred is not 32, the data frame is ignored figure 34 spi interface signal overview 11.2 timing diagrams figure 35 spi signal timing diagram - thresholds = 20% / 80% 30 29 28 27 30 29 28 27 msb msb 6 5 4 3 2 1 lsb 6 5 4 3 2 1 26 8 26 8 7 7 so si csn sclk time lsb cs sclk si t csn( l e a d ) t csn( td ) t csn( la g ) t scl k( h) t scl k( l ) t scl k( p) t si( su ) t si( h ) so t so( v) t so(en) t so( dis) vih vil vih vil vih vil vih vil
data sheet 51 rev 1.0, 2015-03-27 - TLE82452-3SA serial peripheral interface (spi) 11.3 electrical charact eristics spi interface table 11 electrical characteristics: spi v bat = 8 v to 17 v, v ddx = 4.75 v to 5.25 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. serial clock frequency f sclk ??8mhz 1) 2) 1) not subject to production test, specified by design. 2) maximum spi clock frequency in the application may be less depending on the load at the so pin and the microcontroller spi peripheral timing requirements. p_11.3.1 serial clock high time t sclkh 50 ? ? ns 1) p_11.3.2 serial clock low time t sclkl 50 ? ? ns 1) p_11.3.3 enable lead time (falling csn to rising sclk) t csn_lead 250 ? ? ns 1) p_11.3.4 enable lag time (falling sclk to rising csn) t csn_lag 250 ? ? ns 1) p_11.3.5 transfer delay time (rising csn to falling csn) t csn_td 5??cycles f sys cycles 1) p_11.3.6 data setup time (required time si to falling sclk) t si_su 20 ? ? ns 1) p_11.3.7 data hold time (required time falling sclk to si) t si_h 20 ? ? ns 1) p_11.3.8 output enable time (falling csn to so valid) t so_en ??200nsc l = 200 pf 1) p_11.3.9 output disable time (rising csn to so tri-state) t so_dis ??200nsc l = 200 pf 1) p_11.3.10 output data valid time with capacitive load t so_v ??100nsc l = 200 pf 1) p_11.3.11 so rise time t so_r ??50nsc l = 200 pf 1) p_11.3.12 so fall time t so_f ??50nsc l = 200 pf 1) p_11.3.13 input pin capac itance: csn, sclk, si, clk c in ??20pf 1) p_11.3.14 so pin capacitance c so_hiz ? ? 25 pf tri-state 1) p_11.3.15
data sheet 52 rev 1.0, 2015-03-27 - TLE82452-3SA spi registers 12 spi registers 12.1 description of protocol for each command received at the si pin of the spi interf ace, a serial data stream is returned at the same time on the so pin. the content of the so dat a frame is dependent on the command which was received on the si pin during the previous frame. a read command (r/w = 0) returns the contents of the addressed register one spi frame later. the data bits in the read command are ignored. a writ e command (r/w = 1) will write the dat abits in the spi wo rd to the addressed register. the actual contents of that register will be retu rned to the spi master (mic rocontroller) during the next spi frame. the response is not an echo of the data received from the si pin, it is the actual cont ents of the register addressed in the previous spi frame. figure 36 spi protocol each spi message for the TLE82452-3SA has a length of 32 bit. the message from the microcontroller must be sent msb first. the data from the so pin is sent msb first. the response to an inva lid spi message is the ic version and manufacturer id register (icvid). the so data in the frame immediately following a reset condition is the ic version and manufacturer id (icvid) register. r message #1 w message #2 message #3 r response #1 csn si so response #2
data sheet 53 rev 1.0, 2015-03-27 - TLE82452-3SA spi registers 12.2 icvid register icvid ic version and manufacturer id reset value: 00c1 xx00 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w0000000 manufacturer id 1514131211109876543210 version not used wds field bits type description r/w 31 rw read / write bit 0 = read 1 = read (cannot write to this register) when reading this register, the r/w bit is 0 manuf id 23:16 r ic manufacturer id 1100 0001 = infineon version 15:8 r ic version c11 step = 0000 0110 wds 1r clk watchdog status 0 = clk signal ok or watchdog disabled (reset value) 1 = watchdog timeout fault (cleared only by reset)
data sheet 54 rev 1.0, 2015-03-27 - TLE82452-3SA spi registers 12.3 configuration register config configuration register reset value: 0100 000x h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w0000001 not used 1514131211109876543210 idiag 2 idiag 1 nu sr2 sr1 nu fme fm2 fm1 nu hl2 hl1 nu field bits type description r/w 31 rw read / write bit 0 = read 1 = write when reading this register, the r/w bit is 0 idiag1-2 15:14 rw set off state diagnostic current 0 = high-side current source is active (reset value) 1 = low-side current source is active sr1-2 12:9 rw set slew rate setting of channel 00 = set the channel slew rate to sr 0 (reset value) 01 = set the channel slew rate to sr 1 10 = set the channel slew rate to sr 2 11 = ignored (previous setting is used) fme 6rw set fault mask for en pin 0 = en pin state does not influence the faultn pin (reset value) 1 = faultn pin is driven low if the en pin is low. fm1-2 5:4 rw set fault mask for channel 0 = channel faults do not influence the faultn pin (reset value) 1 = faultn pin is driven low when a fault is detected on the channel hl1-2 2:1 r hsls2, hsls1 pin status (reset value = state of hsls pins) 0 = highside configuration 1 = lowside configuration
data sheet 55 rev 1.0, 2015-03-27 - TLE82452-3SA spi registers 12.4 diagnosis register diag diagnosis register reset value: 0250 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w0000010crcrstcpuvcpwovb not used re2 re1 1514131211109876543210 nu uv2 uv1 nu ot2 ot1 nu ol off2 ol off1 nu olsb 2 olsb 1 nu ovc2 ovc1 nu field bits type description r/w 31 rw read / write bit 0 = read 1 = read (cannot write to this register) when reading this register, the r/w bit is 0 crc 23 r eeprom crc fault bit 0 = no fault detected (reset value) 1 = fault detected rst 22 r reset bit 0 = no reset detected 1 = reset detected (cleared after register is read) cpuv 21 r charge pump undervoltage shutdown 0 = no fault detected (reset value) 1 = fault detected cpw 20 r charge pump undervoltage warning 0 = no fault detected 1 = fault detected (reset value) ovb 19 r overvoltage on vbat pin 0 = no fault detected (reset value) 1 = fault detected re1-2 17:15 r regulator error 0 = no fault detected (reset value) 1 = fault detected rex bit is set if the commanded current is not reached after 8 pwm periods uv1-2 12:13 r undervoltage on load supply pin 0 = no fault detected (reset value) 1 = fault detected ot1-2 11:10 r over temperature fault bits 0 = no fault detected (reset value) 1 = fault detected
data sheet 56 rev 1.0, 2015-03-27 - TLE82452-3SA spi registers oloff1-2 8:7 r open load fault when channel is off 0 = no fault detected (reset value) 1 = fault detected olsb1-2 5:4 r open load / switch-bypass fault bit 0 = no fault detected (reset value) 1 = fault detected ovc1-2 2:1 r overcurrent fault bit 0 = no fault detected (reset value) 1 = fault detected field bits type description
data sheet 57 rev 1.0, 2015-03-27 - TLE82452-3SA spi registers 12.5 clk-divider register note: following a reset or power-up event, the outputs are disabled until this register has been written to. clk-dvd clock divider register reset value: 0300 0818 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w0000011 not used 1514131211109876543210 not used wden m n fsys div field bits type description r/w 31 rw read / write bit 0 = read 1 = write when reading the register, the r/w bit is 0 wden 12 rw enable clk pin watchdog 0 = disable watchdog (reset value) 1 = enable watchdog the output stages are disabled until the wden bit is set. to operate the device without the watchdog f unction, the wden bit must be set to 1 and then cleared to 0. m 11:6 rw set mantissa of pre-divider (reset value = 32 decimal) fdither = fsys / ((m+1) * 2^n) n 5:2 rw set exponent of pre-divider (reset value = 6) fdither = fsys / ((m+1) * 2^n) fsys div 1:0 rw set f clk / f sys divider 00 - divide by 8 (reset value) 01 - divide by 6 10 - divide by 4 11 - divide by 2 note: autozero should be initiate d after changing the divider, first write to this register after powerup automatically starts the autozero process
data sheet 58 rev 1.0, 2015-03-27 - TLE82452-3SA spi registers 12.6 calibration register cal calibration register reset value: 0500 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w0000101cm not used 1514131211109876543210 not used cal2 cal1 nu field bits type description r/w 31 rw read / write bit 0 = read 1 = write when reading this register, the r/w bit is 0 cm 23 rw enable calibration mode 0 = disable calibration mode (reset value) 1 = enable calibration mode cal2 5:4 rw set load2 output stage state in calibration mode 00 = hs and ls fets off (reset value) 01 = hs fet off, ls fet on 10 = hs fet on, ls fet off 11 = hs and ls fets off cal1 3:2 rw set load1 output stage state in calibration mode 00 = hs and ls fets off (reset value) 01 = hs fet off, ls fet on 10 = hs fet on, ls fet off 11 = hs and ls fets off
data sheet 59 rev 1.0, 2015-03-27 - TLE82452-3SA spi registers 12.7 setpoint register setpoint setpoint register reset value: 1x40 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w0010 not used channel # en al not used 1514131211109876543210 not used setpoint field bits type description r/w 31 rw read / write bit 0 = read 1 = write when reading this register, the r/w bit is 0 channel 25:24 rw channel number 01 = load1 10 = load2 en 23 rw enable channel 1 = enable the addressed channel 0 = disable the addressed channel en cannot be set=1 until the diag register is read auto limit 22 rw enable integrator autolimit for the addressed channel 1 = enable autolimit (reset value) limit=20d and -20d 0 = disable autolimit setpoint 10:0 rw set average current setpoint of addressed channe l (reset value=0) lsb = (1500/2047) ma
data sheet 60 rev 1.0, 2015-03-27 - TLE82452-3SA spi registers 12.8 dither register dither dither register reset value: 1x00 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w0011 not used channel # en sync cfb mode not used 1514131211109876543210 number of dither steps not used dither step size field bits type description r/w 31 rw read / write bit 0 = read 1 = write when reading this register, the r/w bit is 0 channel 25:24 rw channel number 01 = load1 10 = load2 en 23 rw enable dither for the addressed channel 1 = enable dither 0 = disable dither (reset value) sync 22 rw enable synchronization of dither to pwm frequency 1 = enable synchronization - start of dither synched to start of pwm cycle 0 = disable synchronization - free running dither (reset value) cfb mode 21 rw mode for current feedback 1 = min / max / pwm periods per dither period 0 = average current and switching period steps 15:10 rw set the dither steps of the addressed channel (reset value = 0) number of steps in a quarter dither cycle. step duration = 1/fdith step size 5:0 rw set the dither stepsize of addressed channel (reset value = 0) lsb = (1500/2047) ma. note: the product of the steps and step size values must not exceed 1023, ot herwise the dither waveform will be incorrect.
data sheet 61 rev 1.0, 2015-03-27 - TLE82452-3SA spi registers 12.9 integrator limit register int limit integrator register reset value: 2xff ffff h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w0100 not used channel # high limit 1514131211109876543210 high limit (cont) low limit field bits type description r/w 31 rw read / write bit 0 = read 1 = write when reading this register, the r/w bit is 0 channel 25:24 rw channel number 01 = load1 10 = load2 high limit 23:12 rw set high limit of integrator (reset value = 07ffh) effective value is 32 * high limit value low limit 11:0 rw set low limit of integrator (reset value= 07ffh) effective value is -32 * low limit value
data sheet 62 rev 1.0, 2015-03-27 - TLE82452-3SA spi registers 12.10 pwm period register pwm period pwm period register reset value: 2x20 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w0101 not used channel # not used ki_index not used 1514131211109876543210 not used pwm period field bits type description r/w 31 rw read / write bit 0 = read 1 = write when reading this register, the r/w bit is 0 channel 25:24 rw channel number 01 = load1 10 = load2 ki_index 22:20 rw set the ki gain for the pwm period controller ki = 2^-ki_index. maximum value = 6. writing 7 to this field will result in ki_index=6 ki_index reset value = 010 b ki reset value = 1/4 pwm period 11:0 rw set the pwm period lsb = 16 / f sys
data sheet 63 rev 1.0, 2015-03-27 - TLE82452-3SA spi registers 12.11 integrator threshold &open on register integrator threshold & open on register reset value: 3x00 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w0110 not used channel # not used integrator threshold 1514131211109876543210 integrator threshold (cont) open load on limit field bits type description r/w 31 rw read / write bit 0 = read 1 = write when reading this register, the r/w bit is 0 channel 25:24 rw channel number 01 = load1 10 = load2 integrator threshold 21:6 r integrator threshold - read only threshold at which the output stage is turned off. controlled by pwm period controller. reset value = 0 open load on limit 5:0 rw set the open load while on current threshold lsb = (1500/255) ma reset value = 0 must be written with a non-zero va lue to enable open load while on fault detection
data sheet 64 rev 1.0, 2015-03-27 - TLE82452-3SA spi registers 12.12 autozero register autozero autozero register reset value: 3x80 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w0111 not used channel # az start 1514131211109876543210 not used az value field bits type description r/w 31 rw read / write bit 0 = read 1 = write when reading this register, the r/w bit is 0 channel 25:24 rw channel number 01 = load1 10 = load2 az start 23 rw initiate auto zero 1 = start autozero sequence (reset value) 0 = no effect the en bit in the setpoint register must be set to 0 in order to perform the autozero function. az value 12:0 r read the offset of addressed channel (reset value = 0) after the autozero sequence is completed, the az value field will contain the measured offset.
data sheet 65 rev 1.0, 2015-03-27 - TLE82452-3SA spi registers 12.13 feedback register feedback feedback register reset value: 4x00 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r/w1000 not used channel # cal mode - current feedback cfb=0 - current feedback cfb=1 - max current 1514131211109876543210 cal mode - current f eedback (cont) not used cfb=0 current fb (cont) cfb=0 period feedback cfb=1 - min current cfb = 1 - # switching periods in dither cycle field bits type description r/w 31 rw read / write bit 0 = read 1 = read (cannot write to this register) when reading this register, the r/w bit is 0 channel 25:24 r channel number 01 = load1 10 = load2 cal mode current fb 23:8 r cal mode = 1 current feedback lsb = (1500/65535) ma current fb 23:12 r cal mode = 0 & cfb mode = 0 current feedback average load current = 1.5 * current fb / period fb average current measured over the last switching cycle field value = 0 if channel is not operating value set to 00 after read period fb 11:0 r cal mode = 0 & cfb mode = 0 switching period feedback 1 lsb = 16 / f sys period of last switching cycle field value = 0 if channel is not operating max current 23:16 r cal mode = 0 & cfb mode = 1 max current feedback lsb = (1500/127) ma maximum current measured over last dither cycle (dither enabled) maximum current measured since last read of this register (dither off) field value = 0 if channel is not operating value set to 00 after read
data sheet 66 rev 1.0, 2015-03-27 - TLE82452-3SA spi registers attention: max. current, min. current and switching cycles per dither are set as indicated in the spi description min current 15:8 r cal mode = 0 & cfb mode = 1 min current feedback lsb = (1500/127) ma minimum current measured over la st dither cycle (dither enabled) minimum current measured since last read of this register (dither off) field value = 0 if channel is not operating value set to ff after read switching cycles per dither cycle 7:0 r cal mode = 0 & cfb mode = 1 switching cycles per dither cycle 1 lsb = 1 switching cycle field value = 0 if channel is not operating or dither is disabled value set to 00 after read field bits type description
data sheet 67 rev 1.0, 2015-03-27 - TLE82452-3SA application information 13 application information this is the description how the ic is used in its environment? note: the following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. figure 37 application diagram - low-side configuration application circuit ls52.vsd control c e .g. tc1766 vss spi lsup1 load2 load 1 vcc vbat 5v gpio so sck si csb resn faultn tm en spi lsup2 gndp1 clk hsd e.g. bts5246 - 2l charge pump gpio clkout vbat gndp2 gndp lsup cpout supply vdda gnda vddaref gndaref vddd gndd vio tst0 hsls2 hsls1 cpc1l cpc1h cpc2h cpc2l power supply 100 nf 27 nf 27 nf 220 nf 100nf 100nf 100nf 100 nf 10k tm02 tmo1 5v ~100uf resn nu 4.7nf to 10nf
data sheet 68 rev 1.0, 2015-03-27 - TLE82452-3SA application information figure 38 application diagram - high-side configuration note: this is a very simplified example of an application ci rcuit. the function must be verified in the real application. 13.1 further application information ? please contact us for information regarding the pin fmea ? for further information you may contact http://www.infineon.com/ application circuit hs52.vsd control c e .g. tc1766 vss spi lsup1 load2 load 1 vcc vbat 5v gpio so sck si csb resn faultn tm en spi lsup2 gnndp clk hsd e.g. bts5246 - 2l charge pump gpio clkout vbat gndp1 gndp2 lsup cpout supply vdda gnda vddaref gndaref vddd gndd vio hsls2 hsls1 tst0 cpc1l cpc1h cpc2h cpc2l power supply 100 nf 100 nf 27 nf 27 nf 220 nf 100nf 100nf 100nf 100 nf 10k tm02 tmo1 ~100uf resn nu 4.7nf to 10nf
data sheet 69 rev 1.0, 2015-03-27 - TLE82452-3SA package outlines 14 package outlines figure 39 pg-dso-36 green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). bottom view 1) does not include plastic or metal protrusion of 0.15 max. per side 2) stand off 1 18 0.25 ?.1 pg-dso-36-10, -12, -15, -16, -21, -23, -26, -27 v01 1.1 36 +0.13 0.25 36x 19 m (heatslug) 15.74 0.65 17 x 0.65 = 11.05 ?.1 c ab 19 c 3.25 3.5 max. +0.1 2) 0 0.1 ?.1 36 2.8 b 11 ?.15 1) 1.3 5? 0.25 ?? -0.02 +0.07 6.3 14.2 ?.3 b ?.15 0.25 heatslug 0.95 heatslug ?.1 5.9 3.2 ?.1 13.7 18 1 -0.2 index marking 15.9 1) ?.1 a 1 x 45? for further info rmation on alternative pa ckages, please visit our website: http://www.infineon.com/packages . dimensions in mm
TLE82452-3SA revision history data sheet 70 rev 1.0, 2015-03-27 - 15 revision history trademarks of infineon technologies ag aurix?, c166?, canpak?, ci pos?, cipurse?, econopac k?, coolmos?, coolset?, corecontrol?, crossav e?, dave?, di-pol?, easypim?, econobridge?, econodual?, econopim?, econopack?, eicedriver?, eupec?, fcos?, hitfet?, hybridpack?, i2rf?, isoface?, isopack?, mipaq?, modstack?, my-d?, novalithic?, optimos?, origa?, powercode?; primarion?, pr imepack?, primestack?, pr o-sil?, profet?, rasic?, reversave?, satric?, si eget?, sindrion?, sipmos?, smartl ewis?, solid flash?, tempfet?, thinq!?, trenchstop?, tricore?. other trademarks advance design system? (ads) of agilent te chnologies, amba?, arm?, multi-ice?, keil?, primecell?, realview?, thumb?, vision? of arm limited, uk. autosar? is licensed by autosar development partnership. bluetooth? of bluetooth sig inc. cat-iq? of dect forum. colossus?, firstgps? of trimble navigation ltd. emv? of emvc o, llc (visa holdings in c.). epcos? of epcos ag. flexgo? of microsoft corp oration. flexray? is licensed by flexray consortium. hyperterminal? of hilgraeve incorporated. iec? of commission electrot echnique internationale. irda? of infrared data association corporation. iso? of international organization for standardization. matlab? of mathworks, inc. maxim? of maxim integrated products, inc. microtec?, nucleus? of mentor graphics corporation. mipi? of mipi allianc e, inc. mips? of mips technologies, inc., u sa. murata? of murata manufacturing co., microwave office? (mwo) of applied wave research inc., omnivision? of omnivision technologies, inc. openwave? openwave systems inc. red hat? red hat, inc. rfmd? rf micro devices, inc. sirius? of si rius satellite radio inc. solaris? of sun microsystems, inc. spansion? of spansion llc ltd. symbian? of symbian software limited. taiyo yuden? of taiyo yuden co. teaklite? of ceva, inc. tektro nix? of tektronix inc. toko? of toko kabushiki kaisha ta. unix? of x/open company limited. verilo g?, palladium? of cadence design systems, inc. vlynq? of texas instruments incorpor ated. vxworks?, wind river? of wind ri ver systems, inc. zetex? of diodes zetex limited. last trademarks update 2011-11-11 revision date changes 1.0 2015-03-17 initial data sheet
edition 2015-03-27 published by infineon technologies ag 81726 munich, germany ? 2015 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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